LCDM Engineering is committed to the advancement of HDL ASIC/FPGA design through training and custom design services.
Mr. Mills is a senior hardware design engineer
with over 20 years of experience. During this time he has worked on
numerous ASICs including CMOS devices, ECL devices (137 MHz and 274
MHz), and a high voltage (15 volt) mixed analog/digital device.
Mr. Mills has employed top-down design methodology for over 12 years and is
proficient in Verilog, SystemVerilog, and VHDL. Mr. Mills has developed and implemented top-down ASIC design flows for a
number of companies. His specialty is design tool integration and
design tool flow automation. Through his work in developing and
integrating top-down design flows, he has taught a number of
methodology classes, which include ASIC design flow, Verilog,
SystemVerilog, VHDL, Synopsys synthesis, DFT, BSD (1149.1), and
makefile automation. Mr. Mills is a certified
instructor of Verilog and SystemVerilog courses for Sutherland HDL, Inc., and Sunburst
Design, Inc..
Mr. Mills has served as Technical Chair for many SNUG Conferences (Synopsys
Users Group). Please refer to RESUME for a detailed
listing of the conferences.
Mr. Mills has authored and co-authored several papers. Please refer
to PAPERS for a complete listing
of titles, and links to the full text.
Mr. Mills has worked for L3 Communications, US Robotics,
Honeywell, Microchip, and a number of other companies. He holds a
Bachelor of Science in Electrical Engineering from Brigham Young
University, and is a member of IEEE.
Mr. Mills is frequently out of the office teaching around the country. To ensure your message gets to him, please send an email to the address below.