LCDM Engineering is committed to the advancement of HDL ASIC/FPGA design through training and custom design services.
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- VHDL VERILOG Training
- Methodology Training
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Published Papers
- DVCON 20: Systemverilog Configurations and Tool Flow Using SCons (an Improved Make) and (Slides)
- DVCON 15: SystemVerilog Assertions for Clock-Domain-Crossing Data Paths (Slides Only)
- DVCON 14: Can My Synthesis Compiler Do That? What ASIC and FPGA Synthesis Compilers Support in the SystemVerilog-2012 Standard and (Slides)
- Mentor 13: Being Assertive With Your X (SystemVerilog Assertions for Dummies) ( Slides only )
- SNUG 13 : Synthesizing SystemVerilog (Busting the Myth that SystemVerilog is only for Verification)
- SNUG 12 : Yet Another Latch and Gotchas Paper and ( Slides )
- Mentor 09: If Chained Implications in Properties Weren't So Hard, They'd be Easy ( Slides only-including Mentor ATV screen shots )
- SNUG 09 : If Chained Implications in Properties Weren't So Hard, They'd be Easy (Tricky SVA Properties Made Easy)
- SNUG 07 : Gotcha Again--More Subtleties in the Verilog and SystemVerilog Standards that Every Engineer Should Know
- SNUG 06 : Standard Gotchas--Subtleties in the Verilog and SystemVerilog Standards that Every Engineer Should Know
- SNUG 06 : SystemVerilog Assertions are for Design Engineers Too!
- SNUG 04 : Being Assertive With Your X (SystemVerilog Assertions for Dummies)
- SNUG 03 : Synchronous Resets & Asynchronous Resets Design Techniques--Part Deux
- SNUG 03 : HDVL += (HDL & HVL) SystemVerilog 3.1 - The Hardware Description AND Verification Language
- SNUG 02 : Synchronous Resets? Asynchronous Resets? I Am So Confused! How Will I Ever Know Which to Use?
- SNUG 01 : Getting the Most Out of the New Verilog-2000 Standard
- SNUG 00 : Habits of Deficient ASIC Design
- SNUG 99 : RTL Coding Styles That Yield Simulation and Synthesis Mismatches
- SNUG 97 : Synthesis of a Million-Gate ASIC